Tutorial Speakers

Circuit Design for Scalable Quantum Computing

Jae-Yoon Sim

Abstract:

The milestones of quantum computing predicts an exponential growth in the number of physical qubits. As the qubits in the dilution refrigerator should be individually controlled, the scaling of the control electronics also gives challenges and opportunities in the field of engineering of integrated circuits. This tutorial reviews operating principles of superconducting qubits, as one of the most promising quantum devices for the scalable fault-tolerant quantum computing, and introduces circuit design considerations for high-quality control and readout of the qubit states using integrated cryo-CMOS SoC operating at 4K.

Biography:

   Jae-Yoon Sim received the B.S., M.S., and Ph.D. degrees from the Pohang University of Science and Technology (POSTECH), in 1993, 1995, and 1999, respectively. From 1999 to 2005, he was a Senior Engineer with Samsung Electronics. Dr. Sim joined POSTECH in 2005 and is currently a professor. Since 2019, he has been the Director of the Scalable Quantum Computer Technology Platform Center. His research interests include sensor interface circuits, high-speed serial/parallel links, phase-locked loops, data converters, neural networks and cryo-CMOS circuits for quantum computing. He received Takuo-Sugano Award in 2002, and Jan Van Vessem Award in 2023 from ISSCC. In 2020, he received the Scientist of the Month Award in Korea. He has served on the Technical Program Committees for ISSCC, Symposium on VLSI Circuits, and ASSCC.

Masum Hossain

Carleton University

Abstract:

Multilevel signaling has extended the lifeline of wireline links beyond 100 Gb/s. But it’s SNR penalty has mandated much more sophisticated equalization that is more suitable for digital implementation. This tutorial aims at bridging the gap between well-understood analog/mixed-signal solutions and today’s DSP-based solutions. Starting from traditional analog architectures, this talk will walk through the evolution toward today’s DSP-based equalization and provide the background for tomorrow’s sequence decoding.

Biography:

Masum Hossain received the B.Sc. degree from the Bangladesh University of Engineering and Technology, Dhaka, Bangladesh, in 2002, the M.Sc. degree from Queen’s University, Kingston, ON, Canada, in 2005, and the Ph.D. degree from the University of Toronto, Toronto, ON, in 2010. From 2007 to 2013, he worked in product development and industrial research, focusing on high-speed link design in multiple organizations, including Gennum and Rambus. In 2013, he joined the Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada. Recently in 2023, he joined Carleton University in Ottawa, Canada. Dr. Hossain received the Best Student Paper Award at the 2008 IEEE Custom Integrated Circuits Conference and the Analog Device’s Outstanding Student Designer Award in 2010. In 2021 he received EPS society nominated best paper award in IEEE Transaction in Components, Packaging and Manufacturing.

Reconfigurable ML Processor: Fundamental Concepts, Application, and Future Trends

Shouyi Yin

Tsinghua University

Abstract:

A reconfigurable ML processor increases hardware flexibility to accommodate various ML algorithms and speeds up processing time while consuming less power. Typically, a reconfigurable ML processor includes multiple reconfiguration hierarchies, such as chip-level, processing element array-level, and processing element-level reconfigurations. Chip-level reconfiguration dynamically adjusts the parallelism of multi-chip systems to minimize computation latency and data access. Processing element array-level reconfiguration changes the dataflow or mapping of the computing engine to fully reuse the on-chip data, reducing the memory access. Processing element-level reconfiguration changes the function of the computing unit, such as computing precision and sparsity processing pattern, to increase the bit-wise hardware utilization. This tutorial explores the fundamental concepts of reconfigurable technology, discusses its applications in both digital and analog ML processors, and prospects for future development trends in reconfigurable technology.

Biography:

Shouyi Yin received the B.S., M.S., and Ph.D. degrees in electronic engineering from Tsinghua University, Beijing, China, in 2000, 2002, and 2005, respectively. He has worked with Imperial College, London, U.K., as a Research Associate. He is currently a full professor and the vice director of School of Integrated Circuits in Tsinghua University. His research interests include reconfigurable computing, AI processors and high level synthesis. He has published more than 100 journal papers and more than 50 conference papers. He has served as technical program committee member in the top VLSI and EDA conferences such as A-SSCC, MICRO, DAC, ICCAD and ASPDAC. He is the associate editor of IEEE TCAS-I, ACM TRETS and Integration, the VLSI journal.